The following are standard volume production process windows. Actual feasibility of high-end board types requires combined evaluation of stackup, structure and process mix — our engineering team gives clear conclusions at the quoting stage.
Complete capability range from double-sided prototypes to 32-layer high multilayer, heavy copper and specialty structures.
| Structure & dimensions (STRUCTURE) | |
|---|---|
| Layer count range | 2 – 32 layers |
| Max. fabrication size | 610 × 1100 mm |
| Min. finished board size | 5 × 5 mm |
| Double-sided board thickness | 0.2 – 6.0 mm |
| Multilayer board thickness | 0.4 – 8.0 mm |
| Board thickness tolerance | ±10% (standard board thickness) |
| Outline tolerance | ±0.10 mm |
| Board warpage | ≤ 0.5% (meets SMT mounting requirements) |
| Traces & copper (TRACE & COPPER） | |
|---|---|
| Min. line width / spacing | 3 / 3 mil (2 / 2 mil for HDI) |
| Inner layer copper thickness | 0.5 – 8 OZ |
| Outer layer copper thickness | 0.5 – 13 OZ (incl. electroplated thickening) |
| Finished copper thickness tolerance | ±10% |
| Impedance control tolerance | ±8% (±10% standard) |
| Measurable impedance types | Single-ended / differential / coplanar waveguide |
| Min. solder mask dam width | 3 mil |
| Min. legend line width | 5 mil |
| Drilling & hole metallization (DRILLING) | |
|---|---|
| Min. mechanical drill diameter | 0.15 mm |
| Min. laser drill diameter | 0.10 mm (HDI blind vias) |
| Max. aspect ratio | 20:1 (25:1 for backplane structures) |
| Hole copper thickness | 25 – 50 μm (thicker plating on request) |
| Hole position accuracy | ±0.05 mm |
| Back drill depth control precision | ±0.05 mm |
| Layer-to-layer registration accuracy | ±0.05 mm |
| Via types | Through / blind / buried / via-in-pad / half-hole |
| Appearance & panel (FINISH & PANEL） | |
|---|---|
| Solder mask color | Green / black / matte black / blue / red / white |
| Legend color | White / black (photoimageable legend optional) |
| Profiling methods | Routing / punching / V-CUT / stamp holes |
| Panelization methods | V-CUT, stamp holes, frameless panelization (evaluated as needed) |
| Finished product inspection standards | IPC-A-600 Class 2 / Class 3 (as required) |
| Packaging method | Vacuum packing + desiccant + humidity indicator cards |
| Barcode / QR code | Surface code, inner layer code, packaging code (traceable) |
| Shipment reports | Microsection, impedance, visual and dimensional reports (on request) |
Key processes and special techniques available to meet the structural needs of high-end board types:
Mechanical buried vias, laser blind vias, stacked vias and via-in-pad (POFV) in combination; 1–3 step HDI structures in stable volume production.
Back drilling removes excess plated hole wall (stub), reducing impedance discontinuities and reflections on high-speed links.
Stepped and long/short gold fingers with bevel edges; slot precision ±0.05 mm.
Up to 13 OZ heavy copper boards, local heavy copper and buried/embedded copper structures balancing current and heat.
Local hybrid lamination of materials with different Dk/Df balances high-frequency performance and cost; metal-base composites supported.
Half-hole and metallized half-hole processes support modular assembly; edge metallization is used for shielding and grounding.
FR-4 and PI hybrid lamination with multilayer rigid-flex structures; static and dynamic flexing designs supported.
Aluminum / copper base boards with thermal separation structures; flush or recessed thermal pads, thermal conductivity 2–12 W/m·K.
Resin plugging, electroplated via filling (POFV) combined with back drilling meet high-density interconnect and planarity requirements.
Choose surface finish by soldering method, storage period and signal requirements; alternatives can be evaluated during engineering.
| Surface finish | Thickness reference | Characteristics | Typical applications |
|---|---|---|---|
| ENIG (electroless nickel immersion gold) | Ni 3–6 μm / Au 0.05–0.2 μm | Good planarity, solderable and wire-bondable, long shelf life | High-density BGA, HDI, communication boards |
| ENEPIG (electroless nickel electroless palladium immersion gold) | Pd 0.05–0.15 μm / Au 0.03–0.1 μm | Handles both soldering and wire bonding, with stronger anti-diffusion capability | Package substrates, high-reliability applications |
| Immersion silver | 0.1–0.3 μm | Low high-frequency loss, good planarity; sulfur protection needed | High-frequency high-speed boards, optical modules |
| Immersion tin | 0.8–1.2 μm | Flat, suited to press-fit and fine-pitch soldering | Press-fit connectors, fine-pitch devices |
| OSP (organic solderability preservative) | 0.2–0.5 μm | Low cost, environmentally friendly; protection decreases after multiple reflows | Standard SMT soldering boards |
| HASL (leaded / lead-free) | 1–40 μm | Low cost, good solderability, poorer surface planarity | Standard boards, through-hole soldering boards |
| Electroplated hard gold (gold fingers) | Au 0.3–3 μm (Ni underlayer) | Wear-resistant, low contact resistance | Gold fingers, connectors, test points |
| ENIG + hard gold combination | Treated by zone | Differentiated treatment of soldering vs. plug-in zones | Optical modules, backplanes |
Standard materials kept in stock; specialty materials supported by per-project procurement and alternative evaluation.
Graded by heat resistance and electrical performance, covering standard multilayer and high-TG needs.
Build high-speed links with low-Df, low-Dk materials, balancing insertion loss and cost.
Copper foil roughness directly affects conductor loss of high-speed signals and must match the frequency.
Metal-base materials boost heat dissipation while maintaining structural strength.
Material combinations for high thermal conductivity and 3D assembly scenarios.
Solder mask type and color affect appearance, precision and assembly identification.
Systematic inspection from incoming material through process to finished product ensures batch consistency and traceability.
| Test / validation items | Method & description | Purpose |
|---|---|---|
| Visual inspection | AOI automated optical inspection + manual visual check | Line nicks, shorts, foreign material and solder mask defects |
| Electrical testing | Flying probe test / dedicated test fixtures | 100% testing for open and short circuits |
| Impedance testing | TDR time-domain reflectometry | Verify impedance values fall within design tolerance |
| Microsection analysis | Hole wall and stackup microsections | Hole copper thickness, interlayer bonding, resin fill condition |
| Ionic contamination | Ionic contamination tester | Assess board cleanliness and long-term reliability risk |
| Thermal shock / thermal cycling | High-low temperature cycling test | Verify hole wall and plating reliability under temperature cycling |
| Solderability testing | Wetting balance / solder float test | Confirm soldering performance after surface finish |
| Final dimensional and visual inspection | 2D measurement + final inspection station | Outline, hole diameter and board thickness per drawing |
| Shipment reports | Microsection / impedance / dimensional reports | Provided per customer requirements; supports incoming audits |
Expedited prototypes and small/medium volume scheduling are arranged separately; committed lead times are given after engineering confirmation.
| Board type / layers | Prototype lead time reference | Small/medium volume lead time reference |
|---|---|---|
| Double-sided boards | 24 – 48 hours | 5 – 8 days |
| 4 – 8 layers | 48 – 72 hours | 7 – 10 days |
| 10 – 16 layers | 5 – 7 days | 10 – 15 days |
| 18 – 32 layers / thick backplanes | 7 – 12 days | 15 – 22 days |
| HDI / blind-buried via structures | 6 – 9 days | 12 – 18 days |
| Heavy copper / metal-base / ceramic | 5 – 10 days | 12 – 20 days |