Bottom line first: once line width and spacing go below 40μm, the yield and precision of subtractive etching start to collapse, and mSAP is the only route that scales. In the 50–75μm window there is no need to rush into mSAP — an improved subtractive process still carries a clear cost advantage. This article sets out the selection boundary between the two routes, the engineering numbers that decide it, and the checks worth running before an order is placed.
Why subtractive etching fails in the fine-line range
Traditional subtractive processing etches panel copper foil, so undercut is unavoidable: as a rule of thumb the undercut is about 0.5–1 times the copper thickness. Etching 60μm lines in 3oz base copper (around 105μm) can produce 50–100μm of undercut, and line-width tolerance generally holds only to ±20% or worse. On 3μm ultra-thin foil the undercut is only 2–3μm, and that is the physical basis on which mSAP holds line-width accuracy to ±8μm. Undercut also produces a trapezoidal cross-section, which raises conductor loss and amplifies the deviation of impedance from the design value — one reason subtractive processing struggles once high-speed designs tighten impedance tolerance to ±8% against the usual ±10%.
The mSAP loop: four steps to watch
1. Ultra-thin foil and carrier selection. The volume mainstream is 3–5μm thin copper, including 1.5–2μm carrier-type thin copper, combined with a low-profile surface (Rz ≤ 1.5μm). Roughness directly sets high-frequency insertion loss, so for 224G links the foil supplier should be asked for profile data.
2. Activation and flash etch. Electroless copper forms a seed layer over the whole surface, dry film defines the pattern, and the copper in non-circuit areas is flashed clean. Over-etching eats into line width, so keep over-etch ≤ 1μm.
3. Pattern plating uniformity. Plating builds the conductor up to 12–15μm, and whole-panel thickness uniformity should be held within ±10%, otherwise both line width and impedance consistency are dragged down. In high-aspect-ratio areas, auxiliary anodes and pulse plating need to be evaluated.
4. Impedance and acceptance data. Fine-line boards must ship with impedance coupons, and the deviation between TDR measurement and design value is accepted against ±8%. Line-width cross-sections should also be sampled to confirm that no base copper remains and that undercut is within limit.
Selection boundary and cost logic
- mSAP is mandatory: BGA escape that requires one track through 0.35mm pitch and below, L/S ≤ 40μm, and RF boards with microstrip width < 50μm where a rectangular cross-section is specified.
- mSAP is not required: L/S between 50–75μm, where an improved subtractive route (5–9μm thin base copper plus high-precision etching) reaches ±8μm accuracy at roughly 20–40% lower cost than mSAP.
- Mixed strategy: a single board can be processed in zones — mSAP in the high-speed area, heavy copper in the power area — which is cheaper than one process across the panel, but feasibility has to be confirmed with the factory at stackup design stage.
Four things to do before ordering
- Compile line width, spacing and impedance target for the critical nets into one impedance control table and submit it with the Gerber, so nothing rests on a verbal agreement.
- Ask the factory to state the minimum line width it can actually hold in mSAP and the tolerance it commits to, and attach that to the contract rather than relying on the figure published on a website.
- At sample stage, already produce and archive cross-sections and TDR reports, so volume production is compared against the same acceptance baseline.
- Use high-Tg, low-loss materials for fine-line stackups; lamination shrinkage is more sensitive there, so validate registration on a small panel before committing to a large batch.
Why the boundary sits where it does
The two routes differ in the number of process steps, not only in the laminate: mSAP adds seed-layer deposition, flash etching and tighter plating control on top of the base flow, and it is those steps that the cost difference pays for. That is why the intermediate band is worth defending with an improved subtractive process, and why a mixed build is often the cheapest way to get mSAP only where the geometry actually needs it. The decision should be made from the finest geometry on the board, not from the average.
Getting the fabricator's engineering review up front matters: asking about stackup, line width, impedance and surface finish in one pass saves a cycle compared with reworking after the prototype. AIPCB.cc offers high-layer-count and fine-line capability — 1–44 layers, a panel size of 610×1100 mm, ±8μm line-width accuracy and ±8% impedance tolerance — and supports that front-loaded review. For complex stackups, send the data to info@ipcba.com.cn or call +86 138 2310 9230 for a manufacturability pre-review.
Send your Gerber files and stackup requirements; a 24-hour expedite channel is available.