Bottom line first: The hard part of a stepped cavity board is not whether a cavity can be milled — it is whether three numbers can be held at once: cavity depth tolerance, residual dielectric thickness under the cavity floor, and assembly-level coplanarity. Controlled-depth routing typically holds ±50 μm, tightening to ±25 μm with per-batch material compensation; below 0.15 mm of residual dielectric the mill-through risk rises sharply; and where a thermal coin meets the cavity, X-ray void area must stay within 5%. These criteria belong on the drawing, not in a post-first-article negotiation.
1. Where cavity boards earn their keep
A cavity lowers a defined region of the board so devices sit below the board surface. Three use cases dominate.
- RF power and front-end modules: bare-die GaN and GaAs devices die-attach to the cavity floor, shortening bond wires by 30%–50% and cutting parasitic inductance and insertion loss together.
- Height-constrained stacks: in camera modules and compact radio units, sinking shields or components 0.8–1.5 mm buys back space for the layer above.
- Direct thermal contact: mating the cavity floor to a heat slug or copper coin cuts thermal resistance 30%–40% versus a "copper foil + thermal via" path.
2. Two process routes — choose by depth
Depth determines the cost structure, and picking the wrong route is the most common waste.
- Post-lamination controlled-depth routing: depth-stopped routers cut on the Z axis, suiting cavity depths of 0.5–2.0 mm; tolerance stacks laminate-thickness variation against routing distortion, landing at ±50 μm standard and ±25 μm after first-article compensation.
- Thin-core pre-lamination layout: placing the cavity region over thin dielectric lets lamination thin it naturally; depth repeatability reaches ±15 μm, but the whole stack-up must be rearranged, so it fits a single high-volume model.
- Hybrid route: stepped routing at the perimeter plus a thin core at the cavity floor balances tolerance and volume consistency — the usual choice for automotive and semiconductor-test boards.
3. Residual thickness: put the mill-through red line up front
The worst controlled-depth failure is piercing the floor or leaving it too thin. Move that red line into stack-up design.
- Residual dielectric thickness: keep at least 0.15 mm; below 0.10 mm the probability of mill-through and of failing hipot rises together. If an inner-layer copper plane remains on the floor, keep 0.035 mm (1 OZ) of copper or more.
- Depth compensation: measure the actual center thickness of each material batch and re-zero the Z axis; this pulls batch depth scatter from ±40 μm down to ±20 μm.
- Ramped cavities: build bond regions as 15°–45° ramps so the wire clears the step edge at 30° or more; gold-wire fatigue failures drop noticeably.
- Cavity edge treatment: leave a 0.1–0.2 mm chamfer or radius to stop chipping when shields are pressed in.
4. Coplanarity and thermal coins: where heat meets assembly
Cavity boards often pair with bonded thermal coins (Coin), and this is where thermal performance and assembly flatness converge — and where disputes start.
- Board flatness: control overall bow and twist at 0.5% of the diagonal — 1.0 mm on a 200 mm diagonal; tighten to within 0.2 mm where bare die attach onto the cavity floor.
- Coin specification: CDA 110 copper, 1.0–2.0 mm thick, bonded into the cavity with silver-filled conductive adhesive or resin; X-ray acceptance limits void area to 5%.
- Thermal comparison: a 1 mm coin bonded directly to the floor beats a 6×3 thermal-via array with 2 OZ foil by roughly 25%–35% in thermal resistance, without consuming routing area.
- Lamination stress: the CTE gap between copper and FR-4 is about 12 ppm/°C; for coins larger than 10×10 mm, leave a 0.3 mm stress buffer around the perimeter.
5. Acceptance criteria: write them into the drawing
- Depth inspection: measure 5 points (four corners plus center) on each batch's first article with a CMM or depth micrometer, record actuals against the tolerance band, then sample 10% of following boards.
- Micro-sections: take one section each at the cavity floor and the ramp transition, checking copper integrity, micro-cracks and resin smear.
- Hipot: with 0.15 mm residual dielectric, judge interlayer withstand at 500 V DC held for 60 s.
- Traceability: log depth compensation values, tool numbers and material batches together, so any anomaly can be traced back across the batch.
AIPCB.cc is operated by Shenzhen Lingxin Technology Co., Ltd. The platform supports up to 44 layers, a maximum processed size of 610×1100 mm, aspect ratios up to 20:1 (25:1 for backplanes), impedance control tolerance of ±8% (±10% standard), trace accuracy of ±8 μm, heavy copper up to 13 OZ, and expedited prototype evaluation. For engineering and quotation, contact info@ipcba.com.cn or +86 138 2310 9230.
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