Bottom line first: thickness out-of-tolerance is rarely caused by insufficient lamination pressure. It is caused by prepreg fill volume and inner-layer copper weight never being budgeted together at the design stage. A 10% shift in dielectric thickness moves 50 Ω single-ended impedance by 4–5%; holding total thickness to ±10% and critical dielectric layers to ±8% costs far less than chasing the lamination profile afterwards. Treating board thickness as something you simply measure after pressing is the most common starting point for scrapping 40-plus-layer lots.
Board tolerance is not the arithmetic sum of layer tolerances
Take a 44-layer board at 3.2 mm finished thickness. With a balanced construction that leaves roughly 0.07 mm of dielectric per layer on average. If every layer ships within ±10%, the worst-case stack exceeds ±0.3 mm — and IPC-6012 Class 3 already demands ±10% on a 3.2 mm board. You cannot derive a good board from good layers, so tolerance has to be reallocated at design: fewer dielectric layers, a separate allowance for heavy-copper layers, and the dielectric over ground and power planes treated as the adjustable margin.
The workable approach is two tables — a nominal thickness table for impedance calculation, and a permitted adjustment window that the laminator uses to compensate against measured inner-layer copper. Moving an inner layer from 1 OZ to 2 OZ adds about 35 μm per layer, which on 44 layers accumulates to the order of 1.5 mm. That is enough to push a board designed for 1 OZ straight into overweight in its 2 OZ version, with not a single number changed on the drawing.
Dielectric thickness is set by resin flow, not by incoming prepreg thickness
The thickness of prepreg after lamination is not its incoming thickness. It equals glass cloth thickness plus whatever resin remains after filling the copper pattern under pressure. The same sheet of 1080 prepreg can end up 20–30 μm thinner over a 70% copper-density area than over bare laminate. That is the direct reason dielectric layers above large copper planes run thin and impedance above them runs high.
On the design side, the countermeasure is a resin-rich or barrier layer over large copper, or a lower-flow prepreg. On the process side, the controllable variables are ramp rate and the point at which pressure is applied. Ramp too fast and the resin is cured before its viscosity drops, leaving thin dielectric and voids; ramp too slow and the resin flows excessively, starving the panel edge and thinning the whole stack. Both directions show up as a thickness failure, but they are fixed in opposite ways.
So lamination stability cannot be judged from how clean the profile looks. It requires three things at once: a thickness map across the panel (nine or fifteen points), a cross-section of the critical dielectric layers, and the edge resin bleed measurement.
Quantify impedance sensitivity to dielectric thickness before setting tolerances
- 50 Ω single-ended microstrip: each 10% increase in dielectric thickness raises impedance by about 4–5%. Holding ±8% impedance means dielectric tolerance inside ±15%, with line width simultaneously tightened to ±8 μm.
- 100 Ω differential: dielectric thickness matters less than for single-ended, but spacing and coupling dominate, and ±10 μm on spacing is a hard constraint that no dielectric adjustment can recover.
- Stripline (inner layer) has dielectric on both sides, so thickness error is averaged and sensitivity is roughly half that of microstrip — one reason high-speed routing prefers inner layers.
- Solder mask thickness is excluded from impedance calculation, but 25 μm of mask over fine lines drops single-ended impedance by 1–2 Ω. Deduct it as a constant in simulation, or measured values will always read low.
Acceptance items and practical actions
- Write nominal dielectric thickness and the permitted adjustment window layer by layer in the stack-up table. Do not stop at total board thickness; total thickness is an outcome, dielectric thickness is the manufacturable quantity.
- Give copper layers of 3 OZ and above their own allowance and measure inner-layer copper before lamination. When 13 OZ and 1 OZ share one stack, accept locally thin dielectric and carry impedance margin accordingly.
- Cross-section the first article at three places: the critical impedance layer, the thinnest dielectric layer, and the heaviest copper layer. Feed the measurements back into the stack-up table as the correction for the next lot.
- Judge total thickness to IPC-6012 Class 3 at ±10%, but tighten press-fit and card-edge zones to ±0.08 mm, otherwise insertion force and coplanarity fail first.
- Replace single-point measurement with a thickness map in volume. One good point does not prove a uniform panel, especially at 610×1100 mm.
- Rerun the lamination compensation after any material lot change. Resin content and flow vary enough between lots to move thickness on an unchanged profile.
Dielectric thickness is the item most often pushed to the fabricator as a "process problem", when in fact its tolerance budget is fixed the moment the stack-up is drawn. Nominal thickness, adjustment window and copper allowance written down at design give lamination a stable target to chase. AIPCB.cc supports up to 44 layers, a maximum panel size of 610×1100 mm, heavy copper up to 13 OZ, line-width accuracy of ±8 μm, impedance tolerance of ±8% (±10% standard), and aspect ratio up to 20:1 (25:1 for backplanes), with 24-hour rush prototypes. For engineering and quotations, contact info@ipcba.com.cn or +86 138 2310 9230.
Send your Gerber files and stackup requirements; a 24-hour expedite channel is available.