Bottom line first: on-device AI is pushing smartphone and laptop mainboards into the pincer of "more compute, no more area," and the demand will not stay at flagship tier — it cascades down the product ladder level by level. For PCB buyers, the task is not forecasting unit sales but reading the process and material steps along this transmission chain, and locking capacity and qualification rhythm for each tier in advance.
How on-device model demand reaches the mainboard
- Compute rises, area does not: on-device models keep raising SoC compute and bandwidth requirements while battery capacity and thermal solutions keep squeezing the area left for the mainboard, so routing density has to be absorbed by higher HDI layer counts and finer lines.
- Power distribution gets more complex: as core voltages drop and transient currents climb, the power tree gains stages; high-current loops and decoupling layouts grow denser, raising the bar for power-integrity planning on the same footprint.
- RF and compute share one board: antenna keep-out zones cannot be surrendered to digital routing; partitioning, isolation, and via stitching between high-speed digital and RF get tighter, and the number of stack-up and impedance options multiplies accordingly.
Process steps: three tiers, three production logics
- Flagship tier: second-order HDI and above, evolving toward any-layer interconnect; line width/spacing trending to 50 μm and below, typically requiring mSAP-class fine-line processes paired with low-loss laminates.
- Mainstream tier: first-order HDI with selective via filling remains the workhorse; the game is volume yield and delivery stability, where lamination and via-metallization parameter drift directly set unit cost.
- Entry tier: four-to-six-layer conventional multilayer with dense routing, competing on price and lead time — but the spread of gigabit-class interfaces is steadily raising the share of controlled-impedance builds even here.
Two new constraints: materials and thermal
- Select laminates by Df, zone by zone: flagship designs migrate toward Mid/Low Loss materials with Df around 0.005; allocate them by interface speed rather than upgrading the whole board, which only burns cost without benefit on slow domains.
- Design the thermal path up front: how vapor chambers and graphite sheets mount consumes board area; thermal via arrays and copper weights must be settled at the stack-up stage, because a retrofitted thermal solution usually means retooling and a second design spin.
Supply structure and capacity windows
- Fine-line capacity keeps consolidating: mSAP and low-loss laminate capacity concentrates among top-tier fabricators, and new-product introduction queues lengthen with order density — qualification windows must be scheduled earlier than instinct suggests.
- Mainstream-tier switching is the cheapest hedge: first-order HDI processes have already been absorbed by many suppliers, so the cost of dual-source validation stays manageable; this tier is the natural place to spread risk.
- Prototype rhythm sets ramp speed: engineering problems from prototype to pilot build should surface as early as possible; score fabricators on DFM responsiveness and engineering support capability, not on unit price alone.
Four calibration tips for buyers
- Build separate HDI-layer, laminate-grade, and impedance lists for flagship, mainstream, and entry tiers — a single spec sheet for everything leads either to over-engineering or to under-delivery.
- Fine-line and low-loss capacity concentrates at the flagship tier; start qualification and prototyping one quarter earlier and keep the yield-ramp risk inside the prototype stage, where it is cheap to fix.
- At the mainstream tier, qualify at least two suppliers with proven, identical process capability and use dual sourcing to hedge against single-line fluctuation.
- Bring thermal and mechanical interfaces to the fabricator's DFM review early in the design, cutting second revisions to a minimum.
The transmission of on-device AI demand is certain; the process window and cost structure of each tier are not. AIPCB.cc supports up to 44 layers, a maximum panel size of 610×1100 mm, heavy copper up to 13 OZ, line-width accuracy of ±8 μm, impedance tolerance of ±8% (±10% standard), aspect ratio up to 20:1 (25:1 for backplanes), and 24-hour rush prototypes. For engineering and quotations, contact info@ipcba.com.cn or +86 138 2310 9230.
Send your Gerber files and stackup requirements; a 24-hour expedite channel is available.