Silicon carbide (SiC) power devices are pushing the PCB supply chain onto two parallel tracks: ceramic substrates (AlN, Al₂O₃) handling chip-level heat, and high-voltage heavy-copper PCBs handling module-level interconnect. Over the past two years, as SiC traction inverters and solar-storage converters ramped, the packaging question has shifted from "does the PCB fit" to "at which level are heat and voltage resolved". For purchasers, understanding this layered structure matters more to project outcomes than squeezing the PCB unit price.
1. Why SiC changed the division of labor for heat and voltage
SiC devices switch fast and tolerate high junction temperatures (commonly 175 °C and above). The direct consequence is higher loss density: packaging must extract heat through a smaller footprint. Conventional FR-4 (thermal conductivity around 0.3 W/m·K) is no longer sufficient directly under the die. The prevailing division of labor: between die and heatsink, a ceramic substrate or bonded-copper ceramic (DBC/AMB, with AlN above 170 W/m·K) provides first-level heat spreading; the PCB carries control, gate-drive and low-voltage interconnect. Procurement bills therefore include both ceramic substrates and PCBs — two categories with different process windows, supplier bases and acceptance criteria, which should never share one RFQ template.
2. Module-level interconnect: heavy copper and high voltage on the PCB side
On drive and busbar transition boards for power modules, requirements concentrate on three points:
- Heavy-copper current capacity. Main power loops typically require 3–6 OZ, busbar transition boards above 10 OZ; this site supports heavy copper up to 13 OZ. The difficulty lies not in plating but in laminate resin fill and etch uniformity — at design review, ask for the fabricator's historical heavy-copper lamination yield data.
- Creepage and clearance. For an 800 V bus, minimum creepage at pollution degree 2 is far larger than on low-voltage boards and must be reserved at routing time per IPC-2221 tables, not revised before shipment. High-voltage designs also commonly specify laminate CTI ≥ 600; write it into the material spec.
- Reflow tolerance and thermal vias. Local board temperatures rise during reflow of large power devices; heavy copper, mixed stacks with aluminum base, or thermal via arrays (0.3 mm drills at 1.0–1.2 mm pitch) are common. Via fill quality determines long-term reliability, so acceptance must include cross-sections.
3. The ceramic-to-PCB interface: three classic purchasing mistakes
- Quoting DBC/AMB as PCB. Ceramic substrates follow a thick-film/co-fired process system, priced by substrate size and copper thickness — not by PCB square-meter logic. Bundling them in one RFQ distorts both quotations.
- Ignoring CTE mismatch. AlN expands at roughly 4.5 ppm/K versus 14–17 ppm/K for FR-4. A ceramic substrate mounted directly onto a large PCB subjects solder joints to shear under temperature cycling. Either design in compliance (flexible interconnects, stress-relief pads) or validate with thermal cycling at the prototype stage.
- Missing acceptance criteria. Accepting PCBs to IPC-6012 Class 3 is industry consensus, but ceramic-substrate acceptance (copper peel strength, substrate yield grading) is often omitted, leaving incoming-lot variation untraceable. Keep the acceptance clauses of the two material categories separate in the RFQ.
4. Trend outlook and purchasing rhythm
Over the next two to three years, SiC penetration will keep rising in traction, solar-storage and charging infrastructure, and power packaging will diverge further: ultra-high power moves toward AMB ceramics with silver-sintered die attach, while mid-power applications stay on standard modules plus high-voltage heavy-copper PCBs. For purchasing rhythm: ceramic substrates, constrained by upstream powder and sintering capacity, justify quarterly frame agreements; heavy-copper PCB capacity is more elastic and suits order-per-batch purchasing, but keep a 24-hour rush prototyping channel open for fast design-iteration loops.
5. Three actionable recommendations
- Split RFQs into "first-level heat spreading" and "module interconnect" lines, mapped to ceramic-substrate and heavy-copper PCB suppliers respectively.
- Fix the power-board RFQ template to include: copper weight of current loops, creepage/clearance requirements, CTI class, and cross-section acceptance points — return any RFQ missing one of these.
- Prototype the first spin with the real stackup and run thermal cycling immediately; do not defer to mass-production rework — SiC failure costs far exceed prototyping cost.
In summary, power PCB purchasing in the SiC era is essentially choosing the right process and supplier for each level of a layered architecture. AIPCB.cc supports 1–44 layer multilayer fabrication with heavy copper up to 13 OZ, maximum panel size 610×1100 mm, and 24-hour rush prototyping, offering stackup review and prototype validation for power-module transition boards and high-voltage interconnects. Contact info@ipcba.com.cn or +86 138 2310 9230.
Send your Gerber files and stackup requirements; a 24-hour expedite channel is available.