Bottom line first: the capacity bottleneck in advanced packaging is shifting from the wafer side toward substrates and test, and the new orders reaching PCB fabricators are no longer about "more layers" but about larger panels, finer lines and tighter flatness. For buyers this means the habit of quoting by area has to change — quoting by process window is the only way to obtain real lead times and yield commitments.
Where the demand structure is tilting
Package formats for compute chips are moving from a single large die to multi-die and chiplet combinations, and interposer and substrate dimensions are rising accordingly. Three engineering consequences follow: panel size is pressing against the 610×1100 mm process limit, layer counts are concentrating above 20, and the requirements for warpage and coplanarity are getting stricter rather than looser, because assembly tolerance has no margin left to allocate to the substrate.
At the same time, power-integrity requirements are bringing heavy copper and buried copper structures back into the mainstream. Current density on AI server boards keeps rising, so 13 OZ class heavy copper combined with vias at aspect ratios above 20:1 has become a routine configuration for power and ground layers. That combination used to be the specialty of a small number of high-multilayer shops; it is now a mainstream RFQ item.
Three real constraints on the supply side
- Press and vacuum lamination capacity: once layer counts go up, lamination cycle time grows almost linearly, and capacity expansion cannot be solved by simply adding drills.
- Registration and inspection equipment: alignment demands on large panels push X-ray target systems and AOI effective field size to their limits, and equipment lead time is a common bottleneck.
- Engineering headcount: engineering review of high-multilayer boards — stackup, impedance, back drilling, copper balance — takes far longer than for ordinary boards, and engineers who can run that review independently are a scarce resource.
Together these three explain why high-end boards show little price elasticity and why lead times are hard to compress. A buyer who ranks only on price can easily end up with a supplier whose real strength is prototyping rather than volume manufacturing.
Actionable adjustments on the purchasing side
Split the RFQ into process groups
Quote in four groups: conventional multilayer (1–8 layers, standard impedance), high multilayer (10–20 layers, impedance tolerance ±8%), ultra-high-layer and large format (above 20 layers or panels over 500 mm), and mixed or special stackups (Rogers, AlN, metal core). Only within a group are quotations actually comparable.
Write capability parameters into the technical agreement
Do not stop at general phrasing such as "per IPC-6012 Class 3". State at minimum: maximum layer count, maximum panel size 610×1100 mm, aspect ratio limit 20:1 (25:1 for backplanes), line width accuracy ±8 μm, impedance tolerance ±8%, heavy copper limit 13 OZ, and the acceptance conditions for 288 °C solder float and thermal cycling. In a later dispute these clauses matter more than the price clause.
Split dual sourcing by process step, not by whole order
A common mistake is to hand the entire board to two suppliers as mutual backup, which forces both to repeat engineering review and first-article qualification. Splitting by process step works better: fine outer-layer traces and back drilling with one supplier, lamination and heavy copper with another, or prototyping and small volume with a quick-turn shop while volume runs at a specialist plant. Switching cost stays controllable, and no single supplier ends up holding all the process know-how.
Three trend judgements worth tracking
- Lead-time divergence will persist: 24-hour expedited prototyping and volume delivery beyond four weeks will coexist for a long time, and expedited capability itself becomes a hard screening criterion.
- Materials gain bargaining power: low-loss laminates and ultra-low-profile copper foil are relatively concentrated in supply, so buyers should lock material grades in advance instead of letting the fabricator substitute freely.
- Engineering front-loading becomes normal: manufacturability review is moving from post-order confirmation to design-stage involvement, and the earlier it starts, the cheaper the design change.
Every industry trend ultimately reduces to three questions: can it be built, how soon, and how stable is the output. AIPCB.cc supports 1–44 layers, a maximum panel size of 610×1100 mm, aspect ratios up to 20:1 (25:1 for backplanes), line width accuracy of ±8 μm, impedance tolerance of ±8%, heavy copper up to 13 OZ and 24-hour expedited prototyping. Send your RFQ list and stackup requirements to info@ipcba.com.cn or call +86 138 2310 9230 for lead times and engineering advice grouped by process window.
Send your Gerber files and stackup requirements; a 24-hour expedite channel is available.