Bottom line first: advanced packaging has split the value of "one motherboard" into "a test chain". The more expensive the die and the more complex the package, the higher the per-system consumption and replacement frequency of test boards and burn-in boards — and these boards are high-layer-count, fine-line, low-volume and lead-time sensitive, which is a completely different supply logic from volume production boards. Layer count, aspect ratio, impedance tolerance and spare-board policy belong in the RFQ and in the acceptance standard, not in a post-mortem.
Why package upgrades push test-board demand up
Three threads are worth watching. First, chiplets and HBM stacking extend the test item list from functional test to known-good-die (KGD), system-level test (SLT) and long burn-in; test time multiplies, and so does the number of boards sitting in the tester. Second, as package density rises the value per die goes up and the fault tolerance of the test stage narrows — one failed channel can scrap a good part, so test boards are pushed toward tighter impedance consistency and lower contact-resistance drift. Third, a burn-in board works at 125–150 °C for a long time and is essentially a consumable, needing scheduled replacement and refurbishment.
Four engineering differences from a production board
- Layer count and aspect ratio: high-density test boards commonly run 20–40 layers with an aspect ratio above 15:1; backdrilling is mandatory to control the stub, otherwise the eye diagram of the high-speed channel narrows visibly.
- Line precision: line width and spacing often reach the 50/50 μm level; beyond the stable window of subtractive etching this requires mSAP or another semi-additive process.
- Impedance consistency: dozens of channels on one board call for ±8% impedance tolerance (±10% on a standard board), and the channel-to-channel spread has to stay small. That is supported by a symmetric stackup and ±8 μm line-width accuracy, not by trimming impedance point by point.
- Temperature and lifetime: a burn-in board sits at 125–150 °C long term, so a material Tg ≥200 °C is recommended, together with attention to the loss of interlayer adhesion and copper peel strength after 1000 hours.
Three traps in purchasing
Benchmarking a test board against a production board. Lots are usually tens to hundreds of pieces, but the process is high-layer, fine-line and multi-variant, so labour per unit area runs far above a volume board. Anchor the price to volume work and the factory will cut first-article verification and the number of test coupons; the cost comes back on the line as a false-fail rate.
Forgetting refurbishment and spares. Service life is limited by probe contact and thermal cycling, so engineering practice is to hold three sets: in service, spare, and in refurbishment. The purchase contract should define the rework scope — connector replacement, line repair, re-finishing — and the acceptance criteria after refurbishment, otherwise the wait for a board will far exceed the board build cycle.
Quoting lead time in weeks when it should be days. A sensible cycle for a high-layer test board is measured in weeks, and expedite capability exists only at a few factories. Split the two channels: new boards take the normal cycle with full verification, while replacement boards use the 24-hour expedite channel to keep the line running.
What engineering and purchasing should actually do
- Build a test-board register, banded by layer count, aspect ratio, minimum line width and impedance requirement, and give only the top band to a factory with capability above 40 layers and backdrilling.
- Draw impedance coupons and test coupons into the panel drawing and keep a sample from every lot, so channel deviation can be traced back later.
- Prefer ENIG for the surface finish and hard gold on connector fingers; OSP shows clear contact-resistance drift after repeated insertion and high-temperature burn-in.
- Agree the cross-section items — wicking, etch-back and barrel separation — with the factory. Test boards are reworked many times, and barrel quality is harder to guarantee than on a new board.
Buy the category, not the square metre
A test board is not "a motherboard in small quantity"; it is a process category of its own, and the way you choose a supplier has to change with it. Judge a supplier on whether it can hold impedance across dozens of channels, whether it can backdrill without damaging the stub geometry, and whether it can document a rework. Ask for the stackup, the channel count and the impedance target to be reviewed together, because these three drive the process route more than the board area does.
AIPCB.cc supports 1–44 layers, a maximum panel size of 610×1100 mm, aspect ratios up to 20:1 (25:1 for backplanes), ±8% impedance tolerance, ±8 μm line-width accuracy and 24-hour expedited prototyping. For test-board and burn-in orders, send the stackup, channel count and impedance requirements to info@ipcba.com.cn or call +86 138 2310 9230 for an engineering review.
Send your Gerber files and stackup requirements; a 24-hour expedite channel is available.