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Surface finish selection and failure control: from ENIG black pad to the solderability window of OSP and immersion tin

Bottom line first: there is no "best" surface finish, only the one that best matches three inputs — soldering process, storage period and downstream operations. Most ENIG failures are not caused by the gold bath itself but by an over-corroded nickel layer forming black pad, while the cost advantage of OSP and immersion tin is cancelled out by storage limits and reflow-cycle ceilings. Writing those three inputs into the specification removes more risk than any amount of finish selection afterwards.

The six mainstream finishes and where each one fits

Black pad: three root causes you can quantify

Black pad appears as brittle fracture along the nickel–gold interface with a dark fracture face; under cross-section the nickel grain boundaries are corroded and continuous nickel oxide is visible. It traces back to three controllable parameters:

A related observation is that on the same board some pads blacken and others do not: near large copper areas such as thermal pads and shield-can pads, the galvanic effect raises local current density and nickel corrosion is more pronounced. The design should avoid sinking gold directly onto large exposed copper areas, or at least flag those locations separately at design review.

Put the three inputs into the RFQ

Four data sets to ask for at acceptance

Surface finish usually enters the specification together with impedance. Impedance tolerance can be held to ±8% against a standard ±10%, line-width accuracy to ±8 μm, across 1–44 layers, finished copper up to 13oz, a maximum panel size of 610×1100 mm and aspect ratios up to 20:1 (25:1 for backplanes), with 24-hour expedited prototyping. Write the finish, the impedance tolerance and the required acceptance data into the RFQ together with the stackup, and you avoid a second round trip.

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