Bottom line first: solder mask on a high-speed board is not a protective coating — it is a dielectric with a Dk and a Df. Ink sitting over a trace adds capacitance to it, pulling single-ended impedance down by several percentage points and pushing insertion loss up. Solder mask therefore has to enter the impedance model at stackup review, rather than being traced back after prototypes return with impedance low across the whole board.
The ink's dielectric constant sits a grade above the laminate
A typical liquid photoimageable solder mask has Dk of about 3.5–4.2 and Df of about 0.02–0.03 at the 1 GHz level, while high-speed laminates themselves are mostly Dk 3.0–3.6 and Df 0.002–0.010. The ink may be only 15–25 μm thick over the trace crown, but it sits tight against the trace, so its contribution to impedance cannot be ignored. One error that recurs in practice: treating the mask layer as "air" or as a software default Dk in the impedance model, after which the modelled value and the TDR measurement part company.
Tenting and opening are two different routes
- Tenting (full ink coverage): protects traces, suppresses dendrites and CAF, and simplifies cleaning; the price is that impedance must be modelled with the ink Dk and loss rises.
- Opening (exposed copper): impedance is easier to control and loss is lower; but oxidation, flux residue and cleaning must be assessed, along with whether the customer requires exposed copper test points.
- A middle course: open the mask over critical differential pairs and over the impedance test area while tenting the rest, or specify a low-loss high-speed solder mask, where Dk can drop to about the 3.2 level.
Thickness uniformity is the hidden variable
Ink thickness over the trace crown depends on line width and spacing: the denser the routing, the thicker the ink builds, and the gap between dense and sparse areas can reach several μm, which produces impedance variation on a single board. Legend printing and a second post-bake also change the degree of cure and therefore the Dk. So an impedance test board cannot carry only one standard line width: place coupons in both dense and sparse areas and confirm uniformity from measured values rather than from the theoretical stackup calculation alone.
Three things to fix in the RFQ and at acceptance
- Impedance tolerance: ±10% is standard; for high-speed links tighten it to ±8%.
- Test state: state whether the coupon was measured tented or opened — the numbers are not comparable across the two states.
- Material definition: name the ink grade or set Dk/Df limits (for example Dk ≤ 3.5 @1 GHz) and require the material datasheet with the shipment.
Line-width accuracy decides whether impedance can be held at all: line-width capability on this line is ±8 μm, and on 60/60 μm fine lines that tolerance already accounts for about a tenth of the line width, making it one of the main sources of impedance spread and something that must be budgeted together with stackup tolerances.
Five workable recommendations
- Bring the ink into the stackup review: take Dk from the supplier's measured data, not from a software default.
- Open the mask over high-speed differential pairs and use low-loss ink, balancing performance against processability.
- Place coupons in both dense and sparse areas of the test board, so uniformity problems surface at prototype stage.
- Write limit, test state and method into the specification, so that supplier and buyer are not each measuring a different number.
- Treat post-bake, legend and any ink grade change as a change: re-verify impedance, and do not accept silent substitution.
Shenzhen Lingxin Technology's high-end line for AI compute boards covers 1–44 layers, finished copper up to 13oz (18oz maximum base copper on outer layers) and a maximum panel size of 610×1100 mm, with aspect ratios up to 20:1 (25:1 for backplanes) and lead times as fast as 24-48 hours, subject to product complexity, including 24-hour expedited prototyping. For projects involving high-speed impedance and a solder mask system, give the stackup, the ink requirement and the impedance acceptance basis in one review so they align in a single pass.
Send your Gerber files and stackup requirements; a 24-hour expedite channel is available.