Bottom line first: on a 224G link, "buy a more expensive low-loss laminate" is usually not the first priority — what is genuinely underestimated is copper foil roughness. It sets the multiplier on conductor loss, and that multiplier saturates as frequency rises. The decision is therefore not "buy the smoothest foil" but push the ratio of Rz to skin depth into the 1–2 band; past that knee, further foil upgrades give rapidly diminishing returns while lamination adhesion and cost risk go up.
Two halves of the loss, and the ratio flips
Insertion loss is dielectric loss plus conductor loss: dielectric loss rises linearly with frequency, being proportional to f and Df, while conductor loss rises as √f. The higher the frequency, the larger the dielectric share — hence "choose a low-Df material". But conversely, once a low-Df material has pushed dielectric loss down, conductor loss becomes the dominant term, and roughness moves from secondary to primary. The two must be chosen together; optimising only one of them will fail.
Within conductor loss, a rough copper surface lengthens the current path and effectively adds series resistance, expressed in engineering as a roughness correction factor. The key quantity is not the absolute Rz but the ratio of Rz to the skin depth δ:
- δ in copper: about 0.40 μm at 28 GHz and about 0.28 μm at 56 GHz.
- Correction factor: about 1.6 when Rz/δ ≈ 1; it saturates once Rz/δ ≥ 10, with an upper bound of about 2.0.
This explains an observation that is often confused: rough foil has already eaten most of the budget at 10 GHz, because Rz/δ is long since near saturation, while switching to HVLP at 56 GHz gains less than expected — δ is only 0.28 μm there, so a foil with Rz of 0.8 μm also lands near Rz/δ ≈ 3, not far below the saturation ceiling. The higher the frequency, the less "change the foil" is the answer.
Foil grades and the transfer effect
Typical industry magnitudes, for positioning rather than as absolute values: standard foil around Rz 5–8 μm; reverse-treated foil (RTF) around 2–3 μm; the HVLP family converging below 1 μm by generation, with HVLP4 already in the 0.5 μm class. What actually sets loss, however, is the effective roughness after lamination: resin biting into the foil topography transfers it to the interface, so the real value has to be taken after pressing rather than from the raw foil datasheet.
That leads to a second trap: surface treatment (brown oxide or black oxide) and low-roughness foil constrain each other. The job of brown oxide is to bite, and bite comes from micro-roughness; pairing a low-roughness foil with a high-bite treatment hands back the smoothness that was just paid for. Low-roughness foil should be matched with a chemical-bonding treatment whose roughness increase stays in the sub-micron range.
Three points in the stackup that are often missed
- The reference-layer foil counts too: return current flows close to the reference plane, and roughness on that plane contributes conductor loss as well — changing only the signal layer is incomplete.
- Solder mask: the thickness and Df of the mask over high-speed traces affect loss and impedance, so control the thickness in high-speed areas or open the mask locally as the stackup requires.
- Glass cloth style: weave causes local Dk ripple, which in turn affects impedance consistency and differential skew; use flattened or spread glass in high-speed areas and review it together with the foil choice.
Acceptance has to land on a measurable basis
Roughness cannot be backed by an incoming inspection report alone; measure insertion loss with a VNA and a differential test coupon, using the delta-insertion-loss (IEEE 370) method to remove fixture effects, reading at 10 / 20 / 28 / 40 / 56 GHz. The coupon must share the product's stackup, foil and surface treatment, with a TDR trace alongside to check impedance continuity. When the target goes into the specification, state it in dB/inch or dB/mm — not a sentence saying "low-loss material".
Five workable recommendations
- Compute Rz/δ before choosing a foil grade: where Rz/δ is already ≥10, the money belongs in shorter stubs, shorter traces and a lower-Df material, not in chasing HVLP.
- Upgrade signal and reference layers as a pair; do not change only half the stackup.
- Low-roughness foil must be matched with a low-bite brown oxide, then effective roughness re-measured after lamination — or loss measured directly.
- Lock four items into the specification together: Df, foil Rz grade, post-lamination treatment and insertion-loss target by frequency point.
- Give the stackup, link length and target loss at enquiry stage so that material and process window are fixed during prototyping.
Shenzhen Lingxin Technology's high-end line for AI compute boards covers 1–44 layers, finished copper up to 13oz (18oz maximum base copper on outer layers) and a maximum panel size of 610×1100 mm, with lead times as fast as 24-48 hours, subject to product complexity. For high-speed products, provide the target insertion loss and the stackup together when asking for a quotation, so material and lamination route align in one pass.
Send your Gerber files and stackup requirements; a 24-hour expedite channel is available.