Bottom line first: in high-voltage, high-humidity service above 48V, the board that suddenly leaks current three years after installation rarely fails by breakdown — it fails by CAF, conductive anodic filament. It never appears in outgoing test, only after several thousand hours once bias, moisture and an ionic path coexist. What decides life is not cosmetic quality but hole-wall spacing, moisture uptake of the dielectric and the glass/resin interface — all three fixed at the design stage.
Three ingredients: remove one and it never grows
Copper dissolves electrochemically at the anode, migrates through the dielectric and reduces as dendrite at the cathode, bridging two nets meant to stay isolated. The triggers can be listed:
- Bias: a sustained DC potential between adjacent conductors. Risk rises markedly above 48V working voltage; above 300V is a high-risk band.
- Moisture: absorbed moisture raises ionic conductivity. Service above 85%RH, or any condensing condition, multiplies the risk.
- Ionic path: the primary channel is the glass yarn to resin interface; secondary sources are drill smear, protruding glass, insufficient desmear and soluble ions from solder mask residue.
This is why CAF mostly runs hole to hole: drilling severs the glass bundles and exposes interface defects on the wall, so the yarn between two holes becomes the fastest route.
Four quantifiable control points at the design stage
1. Hole-wall clearance — most effective, cheapest. Grade by working voltage: below 48V, ≥0.3 mm is advised; 48~300V, ≥0.4~0.5 mm; 300~1000V, ≥0.8~1.0 mm. This is hole-wall clearance, not hole-centre pitch. Two holes of 0.3 mm diameter on 0.9 mm centres leave only 0.6 mm of clearance, and many reviews fail on that step.
2. Dielectric thickness and creepage distance. Dielectric thickness sets the vertical path length; do not push it below 0.1 mm in high-voltage areas. Keep clearance and creepage distance distinct and take values from IEC 60664-1 by pollution degree and material group. FR-4 CTI usually lands in material group IIIa, and where space is tight, milling a slot between the two nets often beats simply widening the gap.
3. Glass direction. Migration along the yarn is faster than across it. Use flattened or spread glass, or route adjacent conductors at about 15° to the weave to break the continuous yarn channel — this adds almost no cost yet often decides a qualification.
4. Material grade. For high-humidity, high-voltage products choose laminates with Tg ≥ 170 °C and lower moisture absorption, and settle it at stackup review. Changing material after a CAF failure means re-lamination validation and a repeated test programme; that cycle cost far exceeds the price difference.
Five mandatory actions in manufacturing
- Desmear shallow rather than deep: clear drill smear without etching the glass yarn into protrusions — a protrusion is itself a new defect.
- Hole-wall copper: to the IPC-6012 high-reliability reading, average ≥25 μm and minimum ≥20 μm, judged at the lowest point of a metallographic section, not from the average.
- Ionic contamination: hold finished-board cleanliness to ≤1.56 μg NaCl equivalent/cm².
- Degree of cure: verify lamination and solder-mask cure by DSC; incompletely cured resin keeps releasing active species.
- Contamination control end to end: drilling dust, salt from handling and halogenated additives in packaging are all soluble-ion sources.
Acceptance: put CAF into the specification
CAF is a function of time and cannot be screened by a single hipot test. A workable combination is as follows:
- CAF test: per IPC-TM-650 2.6.25, 85 °C / 85%RH with 100 V DC bias, reading insulation resistance at the 500 h and 1000 h points, typical pass threshold ≥10⁸ Ω; the coupon must carry the densest array and tightest spacing in the design.
- Sectioning after biased humidity: look for dendrites on the hole wall and corrosion tracks along the yarn, which locates root cause better than a resistance reading alone.
- Insulation and thermal cycling: set the insulation test by working voltage (a common practice is 2× working voltage + 1000 V), then re-measure after 500~1000 cycles from −40~125 °C.
Five practical recommendations
- Mark the high-voltage net list and working voltage at stackup stage so spacing rules can be checked automatically, not counted by eye.
- Make hole-wall clearance an explicit DRC item and re-check it whenever hole diameter changes.
- Buy margin with the three low-cost levers first: slots, spread glass and angled routing.
- Write CAF conditions and threshold, ionic contamination limit and minimum hole copper into the specification, so an industrial product is not delivered to a consumer-grade reading.
- Give working voltage, long-term humidity and target life at RFQ and run one CAF test at sample stage — it needs 500~1000 h, so the schedule must start early.
Reliability here is about buying time back at the design stage; the RFQ is where that time is protected or lost. Write the clearance-by-voltage table, the CAF condition and threshold, the ionic contamination ceiling and the minimum hole copper into the quotation and acceptance document, with the CAF coupon covering the tightest spacing. Shenzhen Lingxin Technology's high-end line for AI compute covers 1–44 layers, finished copper up to 13oz (18oz outer base copper maximum), a maximum size of 610×1100 mm and a metal-base dielectric thermal conductivity of 2–12 W/m·K, with lead times as fast as 24-48 hours, actual timing depending on product complexity. For these products, supply working voltage and CAF acceptance requirements at quotation so material and process lock in one pass.
Send your Gerber files and stackup requirements; a 24-hour expedite channel is available.