Bottom line first: plated-over-filled via is not one action — moving a via onto a pad — but a closed process loop running from hole-wall quality to fill voiding. What actually decides success is the number of stacked vias and the total dielectric thickness in the stack region, together with the void rate and dimple of the plated fill. The first pair sets signal and mechanical reliability; the second sets BGA joint yield and reliability directly. Meeting any one of those metrics on its own is not enough.
Add up the total thickness before arguing about stacking
The value of POFV is that it invites the via from beside the pad into the pad itself, releasing routing space that vias used to consume. Take a BGA on 0.8 mm pitch: a conventional through-hole design, with its annular ring and diameter allowance, usually occupies more than 0.6 mm square, leaving room for barely a few traces between two pad rows; with POFV the same area releases 30%~50% more routing channels, which is close to decisive for high-density fan-out in advanced HDI.
But the released space depends on the stack actually laminating. The first thing to calculate is total dielectric thickness in the stacked region. A single sheet of standard 1080 prepreg is about 0.06~0.07 mm after lamination, so a four-layer stack still using one sheet of 1080 has too little dielectric and a very narrow window for filling and plating. Experience says a single 1080 is still workable at ≤3 stacked layers; at 4 layers and above, use two sheets of 1080 to build one dielectric layer (about 0.12~0.14 mm), or mix 1078 with 1080, so that each dielectric layer lands above 0.10 mm. That adds board thickness, but it buys enough buffer volume for plated fill, and the void rate can drop from 3%~5% to within 1%.
Voids and dimples: two metrics that must be controlled separately
Many teams treat "the hole is filled" as the only acceptance criterion, which is the easiest trap to fall into. Fill quality has two dimensions:
- Void rate: the volume fraction of cavities left unfilled or encapsulated inside the hole. The common industry criteria are longitudinal void no more than 25% of hole depth and cross-sectional void area ≤5%; for high-reliability products such as server mainboards and automotive boards, ≤3% is advised.
- Dimple: the height by which the filled copper surface sits below the pad surface. IPC-4761 Type VII sets dimple ≤25 μm; for BGA below 0.5 mm pitch with small solder balls, tighten to ≤15 μm, otherwise a gas pocket forms under the ball after reflow and becomes a crack origin in thermal cycling.
The two share a root but not a mechanism. Voids mostly come from insufficient mass transfer of the plating chemistry inside the hole or excessive current density; dimples mostly come from insufficient levelling power of the filling chemistry or insufficient deposit thickness. Merging them into a single "fill completeness" acceptance item is the underlying cause of repeated rework later.
Parameters and acceptance advice you can apply now
Working back from the mechanisms above, a few engineering actions are usable today:
- Dielectric side: at ≥4 stacked layers, build the single dielectric layer in the stack region to above 0.10 mm; arranging the stack centre in reverse, offsetting upper and lower layers, clearly reduces stress concentration.
- Hole side: keep the POFV diameter at ≤0.15 mm and the aspect ratio within 1:1; the shorter the barrel, the more complete the mass transfer of the filling chemistry.
- Plating side: pulse plating (PPR) typically gives a void rate 2~3 percentage points lower than DC plating, but must run at least 2 reversal periods; keep current density at 1.5~2.5 ASD, since higher values worsen voiding.
- Acceptance side: first article needs both metallographic section and X-ray — the section shows void morphology and dimple, the X-ray shows vertical void distribution. Section alone misses through-thickness voids, and X-ray alone cannot measure dimple accurately.
- Before release: put the four items — stacked via count, dielectric grade and thickness per layer, hole diameter and aspect ratio, void rate and dimple limits — into the stackup note and drawing remarks rather than sending a Gerber alone. They drive price and yield, and stating them costs far less than repeated prototyping.
Trade-offs for the design side
POFV buys routing freedom and brings cost and process risk: every extra stacked layer adds lamination cycles and process steps, and hits yield and lead time. Grade its use by necessity — apply POFV only in high-density BGA fan-out areas and on critical signal layers that must be routed through, and keep ordinary blind and buried vias elsewhere. The wider POFV is spread, the narrower the process window and the higher the cost, while the return falls away quickly. The cheapest order is: optimise stackup and dielectric thickness first, then tighten hole diameter and aspect ratio, and only then touch the number of stacked layers. Write the stacked via count, dielectric grade and thickness, hole diameter and aspect ratio, and the void and dimple limits into the RFQ and the acceptance criteria, so the fabricator quotes against the same four numbers you will inspect against.
Send your Gerber files and stackup requirements; a 24-hour expedite channel is available.