Bottom line first: HDI yield problems rarely start at the laser drill. They start where dielectric thickness, via diameter and via filling were never aligned at design stage. A blind-via layout that is only checked for whether it can be drawn tends to lose control of fill dimple and stacked-via registration once it reaches volume. Three numbers carry most of the risk, and all three can be settled before the Gerber is released.
Dielectric thickness sets the ceiling on laser via diameter
CO2 laser via diameter is generally taken at 0.8 to 1.2 times the dielectric thickness. With thin dielectric, a 60 to 80 μm low-loss prepreg for instance, a 100 μm via opens reliably with a stable process window. Holding a small diameter on thicker dielectric raises the number of laser shots required, and the risk of wall charring and damage to the target copper rises with every additional shot. The engineering review should therefore fix the dielectric material and its thickness first, then work back to the blind-via diameter, rather than choosing a diameter and asking the fabricator to make it fit.
The same logic explains why a via table copied from an earlier project often fails on a new stackup. The diameter looks the same on the drawing while the dielectric underneath it has changed, so the energy required to reach the target copper, and the margin left before that copper is damaged, have both moved.
Stacked vias: offset compensation matters more than registration tolerance
1+N+1 and 2+N+2 are the most common HDI structures in current AI module and optical module boards. Stacked vias save space compared with staggered vias, but they demand tighter registration between the layers being joined. In production we recommend the following.
- Reserve at least 25 μm of compensation for the offset between the blind via and the target copper underneath it, so the design absorbs normal process variation instead of consuming the tolerance.
- Keep stacked via positions out of the area directly below BGA pads, and prefer a staggered via combined with plated-over-filled-via, POFV, to release routing space.
- Where laser vias and mechanical vias share a board, drill the mechanical vias before the laser vias, a sequence that keeps the registration datum consistent across both operations.
Via filling: dimple and void are the two red lines
Acceptance for blind-via copper fill normally requires a dimple of ≤ 15 μm, and tighter still where a via is stacked directly on top of the filled one. Two failures are common.
- Voids: the combination of via diameter and board thickness falls outside the filling window of the plating chemistry, or the pulse current parameters do not match that geometry. What the design side can do is avoid blind vias with an aspect ratio greater than 1:1.
- Protrusion: over-grinding after filling damages the dielectric of the adjacent layer, while residual protrusion disturbs the flatness of the next lamination. The process document needs an explicit thickness control point after grinding, not a verbal instruction on the shop floor.
Three recommendations for design engineers
- Bring the full stackup drawing with dielectric thicknesses to the review, instead of only a layer count and a via diameter table.
- Prefer POFV in BGA areas, and cut the blind-via count to the minimum the routing actually needs.
- Before volume release, confirm fill dimple and dielectric thickness on a first-article cross-section, with sampling that covers both board edge and board centre.
Put the three numbers into the RFQ
Dielectric thickness, the ratio between via diameter and dielectric, and the dimple limit after filling are cheap to specify and expensive to discover later. Writing them into the RFQ, together with the stacked or staggered via arrangement and the POFV requirement, gives the fabricator enough information to answer with a real process window instead of a generic capability statement.
Our HDI line holds line-width accuracy to ±8 μm and supports blind and buried vias as well as plated-over-filled-via processing. To have a specific stackup reviewed for feasibility, send the Gerber data and the stackup requirements to info@ipcba.com.cn, including dielectric thickness at each build-up layer and the intended via arrangement.
Send your Gerber files and stackup requirements; a 24-hour expedite channel is available.