Bottom line first: in the loss budget of a 224G link, conductor loss is dominated by copper foil roughness and dielectric loss is decided by the material's Df. Material selection is only the starting point; what actually determines whether the link works is how stable impedance tolerance and roughness remain in volume production. Buying the most expensive laminate does not by itself rescue a link that is lost to process variation.
Match the material grade to the link length
Ultra Low Loss material can cost several times as much as a mid-loss material. Selection should be tiered by link length: short links, such as chip to adjacent connector, are served by mid-loss material that still meets the insertion-loss budget; only long links — across a board or across a backplane — need low-loss or ultra-low-loss grades. Upgrading every net blindly raises cost with only limited improvement in insertion loss, because on a short link the loss is not where the budget is being spent.
Read the other way round, the tiering is also a cost control measure. Once the budget per segment is written down, the grade follows from the number rather than from habit, and the expensive grade is reserved for the segments that genuinely need it.
Judge impedance tolerance by production distribution, not by a single coupon
The hard part of impedance control is not the design value but consistency in volume. Etch undercut, lamination thickness variation and copper thickness deviation all make the actual impedance drift away from the target. When agreeing a tolerance, three things should be made explicit.
- Specify single-ended and differential separately: differential impedance is more sensitive to line width and spacing coupling, so its tolerance should be set on its own rather than inherited from the single-ended figure.
- State the acceptance basis clearly: whether impedance is calculated to IPC-2141A or taken from the supplier's measured TDR report must be noted on the drawing, so that the two sides are not arguing from different definitions.
- Ask for production Cpk: a coupon that meets the target does not mean volume production meets it; request impedance distribution data from actual lots.
Roughness and surface finish move together
At these data rates the current no longer spreads evenly through the copper; it crowds into the surface, so the profile of the foil translates almost directly into extra conductor loss. Low-roughness copper foil (HVLP grade) reduces that loss, but the brown-oxide bonding parameters must be adjusted at the same time; otherwise adhesion drops and peel risk follows. When the foil grade is changed, ask the supplier for adhesion test data in the same package, rather than judging the change by the roughness Ra value alone. A foil that looks better on paper and bonds worse in practice is a net loss on a high-layer board, because the peel risk it carries is a reliability question rather than a cosmetic one.
Executable actions on the design side
- Break the insertion-loss budget down to each link segment, and annotate the material grade and reference tolerance for every segment.
- Deliver an impedance table together with the Gerber data — target value, tolerance and reference layer — to reduce the back-and-forth of confirmation.
- Run simulation against measurement on critical nets, and schedule TDR sampling on the first prototype.
Write the per-segment loss budget, the single-ended and differential impedance tolerances and the acceptance basis into the RFQ and the acceptance document, so that the material grade and the process window are both contractual rather than verbal.
Shenzhen Lingxin Technology Co., Ltd. operates a high-end board line aimed at AI computing, covering 1–44 layers, finished copper up to 13oz (outer-layer base copper up to 18oz) and a maximum panel size of 610×1100 mm, with lead times as fast as 24-48 hours, depending on product complexity. For an engineering review or a quotation, send Gerber data and stackup requirements to info@ipcba.com.cn or call +86 138 2310 9230.
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